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description the CXD1265r generates the timing pulses required by the ccd image sensors as well as signal processing circuits. features ntsc and pal compatible compatible with digital and analog camera systems black-and-white mode compatible (eia/ccir compatible) electronic shutter function h-driver standby function compatible with field/frame accumulation modes * 1 , * 2 * 1 characteristics of ccd image sensor are guaranteed by field accumulation. * 2 low speed shutter can not be used during frame accumulation mode. applications ccd cameras structure silicon gate cmos ic applicable ccd image sensors icx038bna, icx038bnb, icx038bla icx039bna, icx039bnb, icx039bla icx058ak, icx058akb, icx058al icx059ak, icx059akb, icx059al absolute maximum ratings (ta = 25?) supply voltage v dd vss ?0.5 to +7.0 v input voltage v i vss ?0.5 to v dd + 0.5 v output voltage v o vss ?0.5 to v dd + 0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? supply voltage v ee ? to vss v allowable power dissipation p d 500 mw recommended operating conditions supply voltage v dd 5.0 0.25 v operating temperature topr ?0 to +75 ? ?1 CXD1265r e92611c52-st ccd camera timing generator sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin lqfp (plastic) aaa aaa aaa aaa aa aa aa aa aa aa aa aa 8 15 16 17 18 19 20 21 24 25 28 40 56 4 5 6 7 9 11 12 13 14 23 36 61 22 37 41 42 43 44 45 46 57 59 60 62 gate 1/2 vd initialize sync gen 3 10 26 27 29 30 39 38 35 34 31 32 33 47 48 49 50 51 52 53 54 55 58 23 hd initialize 2 64 1 adr . count h ?rom latch adr . count v ?rom latch adr . count rog ?rom latch mode set gate gate driver high-speed pulse generation circuit decoder gate counter shut rom microcomputer controller 63 v ss v dd htsg v ee decoder block diagram
?2 CXD1265r pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 osco osci ef ed0 ed1 ed2 smd1 vss smd2 xvct d1 d2 d3 d4 a5 a4 a3 a0 a1 a2 v ee rg nc v dd v dd h1 h2 vss xsub xv2 xv1 xsg1 xv3 xsg2 xv4 o i i i i i i i o i i i i o o o o o o o o o o o o o o o o inverter output for oscillation. inverter input for oscillation. not used. (with pull-up resistor) shutter speed setting. strobe input for serial mode. (with pull-up resistor) shutter speed setting. clock input for serial mode. (with pull-up resistor) shutter speed setting. data input for serial mode. (with pull-up resistor) shutter mode setting. (with pull-up resistor) gnd shutter mode setting. (with pull-up resistor) not used. (open) fix at low in normal operation. (with pull-down resistor) low: color, high: black-and-white. (with pull-down resistor) low: field readout, high: frame readout * . (with pull-down resistor) low: ntsc/eia, high: pal/ccir. (with pull-down resistor) not used. (open) not used. (open) not used. (open) not used. (open) not used. (open) not used. (open) gnd reset gate pulse output. not used. (open) power supply. power supply for h1 and h2. clock output for ccd horizontal register drive. clock output for ccd horizontal register drive. gnd for h1 and h2. ccd discharge pulse output. clock output for ccd vertical register drive. clock output for ccd vertical register drive. ccd sensor charge readout pulse output. clock output for ccd vertical register drive. ccd sensor charge readout pulse output. clock output for ccd vertical register drive. symbol i/o description * characteristics of ccd image sensor are guaranteed by field accumulation.
?3 CXD1265r 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 test2 mck xshp xshd vss xsp1 xsp2 xsh1/ shp xsh2/ shd xdl1 xdl2 bfg clp1 clp2 clp3 clp4 pblk id wen gm v dd cl ps hd vd htsg test xck ck i o o o o o o o o o o o i/o i/o o o o o i o i i i i i o i test input. set at low in normal operation. ntsc: 910f h , pal: 908f h . clock output. precharge level sample-and-hold pulse. data sample-and-hold pulse. gnd color separation sample-and-hold pulse. halted for black-and-white mode. color separation sample-and-hold pulse. halted for black-and-white mode. switching sample-and-hold pulse/precharge level sample-and-hold pulse (black-and-white mode). switching sample-and-hold pulse/data sample-and-hold pulse (black-and-white mode). delay line clock output. halted for black-and-white mode. delay line clock output. halted for black-and-white mode. pulse output for chroma modulator in encoder. halted for black-and-white mode. clamp pulse output. clamp pulse output. when gm is set at high, standby mode switching input. clamp pulse output. when gm is set at high, standby mode switching input. clamp pulse output. blanking cleaning pulse output. line identification output. halted for black-and-white mode. write enable output for low-speed shutter operation. low: analog signal processing, high: digital signal processing. (with pull-down resistor) power supply. ntsc/eia: 910f h , pal/ccir: 908f h . clock output. switching for electronic shutter speed input method. (with pull-up resistor) low: serial input, high: parallel input. horizontal synchronizing signal input. vertical synchronizing signal input. (during low, 9h for ntsc and 7.5h for pal) control input for xsg1 and xsg2. (with pull-up resistor) low: xsg1, xsg2 halted, high: xsg1, xsg2 generated. test input. set at low in normal operation. (with pull-down resistor) ntsc/eia: 1820f h , pal/ccir: 1816f h . clock output. ntsc/eia: 1820f h , pal/ccir: 1816f h . clock input. pin no. symbol i/o description
?4 CXD1265r electrical characteristics dc characteristics (v dd = 5v 0.25v, topr = ?0 to +75?) item supply voltage v dd v ih1 v il1 v ih2 v il2 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh4 v ol4 r fb r pu r pd i dd i oh = ?ma i ol = 4ma i oh = ?ma i ol = 8ma i oh = ?ma i ol = 8ma i oh = ?ma i ol = 1ma v in = vss or v dd v il = 0v v ih = v dd v dd = 5v icx058ak in normal operating state 4.75 0.7v dd 2.2 v dd ?0.5 v dd ?0.5 v dd ?0.5 v dd /2 500k 40k 40k 5.0 2m 100k 100k 74 5.25 0.3v dd 0.8 0.4 0.4 0.4 v dd /2 5m 250k 250k v v v v v v v v v v v v v ma input voltage 1 (input pins other than those below) input voltage 2 (pins 59 and 60) output voltage 1 (output pins other than those below) output voltage 2 (pins 22, 37, 38, 39, 57, and 63) output voltage 3 (pins 26 and 27) output voltage 4 (pin 1) feedback resistor pull-up resistor pull-down resistor current consumption symbol conditions min. typ. max. unit i/o pin capacitances (v dd = v i = 0v, f m = 1mhz) item input pin capacitance output pin capacitance i/o pin capacitance c in c out c i/o 9 11 11 pf pf pf symbol min. typ. max. unit * power consumption: 370mw typ., icx058 load (in normal operating state)
?5 CXD1265r description of operation 1. mode control symbol gm * 2 ps ef htsg d1 d2 * 2 d3 d4 55 58 3 61 11 12 13 14 analog signal processing digital signal processing serial shutter parallel shutter speed setting speed setting fix at high in normal operation xsg1, 2 xsg1, 2 off on fix at low in normal operation color black-and-white field readout frame readout * 1 ntsc/eia pal/ccir pin no. l h * 1 characteristics of ccd image sensor are guaranteed by field accumulation. * 2 operation with gm = high and d2 = high (black-and-white digital signal processing) cannot be used.
?6 CXD1265r 2. changes in i/o signals in each mode symbol gm d2 test2 xsp1 xsp2 xsh1 xsh2 xdl1 xdl2 bfg clp2 clp3 id 55 12 36 41 42 43 44 45 46 47 49 50 53 l l l color separation sample-and-hold pulse output color separation sample-and-hold pulse output switching sample- and-hold pulse output switching sample- and-hold pulse output delay line clock delay line clock burst flag gate pulse output clamp pulse output clamp pulse output line identification output h l l halted at high halted at high halted at low halted at low halted at high halted at low burst flag gate pulse output (normally not used) standby control input low: standby high: normal operation standby control * low: all circuits halted for standby mode high: only cl output for standby mode line identification output h l h color separation sample-and-hold pulse output color separation sample-and-hold pulse output switching sample- and-hold pulse output switching sample- and-hold pulse output halted at high halted at low burst flag gate pulse output (normally not used) standby control input low: standby high: normal operation standby control * low: all circuits halted for standby mode high: only cl output for standby mode line identification output l h l halted at high halted at high precharge level sample-and-hold pulse output data sample-and- hold pulse output halted at high halted at low halted at low clamp pulse output clamp pulse output (phase change) halted at low pin no. analog color digital color 1 digital color 2 analog b/w * when clp2 = high, normal operation occurs regardless of whether clp3 is high or low. (mode combinations other than those shown above cannot be used.) note) in the standby mode described above, xck, xsg1, xsg2, xv1, xv2, xv3, xv4, xsub, h1, h2, rg, xshd, xshp, xsp1, xsp2, xsh1, xsh2, xdl1, and xdl2 pins are halted at low. mck, clp1, clp4, pblk, id, xvct, wen, bfg, a0, a1, a2, a3, a4, and a5 pins are halted at the state just before standby.
?7 CXD1265r 3. electronic shutter smd1 smd2 l l flickerless: eliminates fluorescent frequency-induced flicker. l h high-speed shutter: shutter speed faster than 1/60 (ntsc), 1/50 (pal) h l low-speed shutter: shutter speed slower than 1/60 (ntsc), 1/50 (pal) h h no shutter operation ps = high: parallel input; set by ed0 to ed2, smd1, and smd2. ps = low: serial input; set by inputting ed0 (strobe), ed1 (clock), and ed2 (data) to each pin. 3-1. parallel input (ps = h) shutter speed compatibility chart mode off x ntsc pal ntsc pal x x x x x x x x x x x x x x x h l l l l l l l l l l l h h h h h h h h h l l h h h h h h h h h l l l l l l l l x x x h h l h l h l h l h l h l h l h l x x x h h h l l h h l l h h l l h h l l x x x h h h h h l l l l h h h h l l l l shutter off 1/100 (s) 1/120 (s) 1/60 (s) 1/50 (s) 1/125 (s) 1/250 (s) 1/500 (s) 1/1000 (s) 1/2000 (s) 1/4000 (s) 1/10000 (s) 2fld 4fld 6fld 8fld 10fld 12fld 14fld 16fld flickerless high-speed shutter low-speed shutter * ntsc/pal smd1 smd2 ed0 ed1 ed2 shutter speed * during frame accumulation mode, low speed shutter data set to ed0 to ed2 are all invalid. shutter speed is 1/30s for ntsc; 1/25s for pal.
?8 CXD1265r 3-2. serial input (ps=l) for serial input (ps = l), smd1 and smd2 bits within ed2 (data) take priority over smd1 (pin 7) and smd2 (pin 9) pins as smd1 and smd2 (shutter mode control). in this case, control by smd1 and smd2 pins is invalid. ed1 (clk) ed2 (data) ed0 (stb) d0 d1 d2 d3 d4 d5 d6 d7 d8 smd1 smd2 dummy ed2 data is latched to the register at the rise of ed1, and transferred to the within during the low period of ed0.
?9 CXD1265r 3-4. low-speed shutter timing chart (during field accumulation mode) oe oeo eoe oeo eoe vd xsg1, 2 wen (ed2 : ed1 : ed0 = h : h : h) xsg1, 2 wen (ed2 : ed1 : ed0 = h : h : l) ts 2 th 2 tw 1 tw 1 ts 1 ts 0 tw 0 ed2 ed1 ed0 symbol t s2 t h 2 t s1 t w0 t s0 t w1 20ns 20ns 20ns 20ns 20ns 20ns 50s ed2 set-up time, activated by the rising edge of ed1 ed2 hold time, activated by the rising edge of ed1 ed1 rising set-up time, activated by the rising edge of ed0 ed0 pulse width ed0 rising set-up time, activated by the rising edge of ed1 ed1 pulse width (serial input) min. max. ac characteristics (during frame accumulation mode) xsg1, 2 wen (ed2 : ed1 : ed0 = x : x : x) (fixed at h)
?10 CXD1265r 3-5. shutter speed calculation formula 1. high-speed shutter ntsc (l 16 = load value) t = [262 10 ?(1ff 16 ?l 16 ) ] 63.56s + 34.9s pal (l 16 = load value) t = [312 10 ?(1ff 16 ?l 16 ) ] 64.00s + 35.0s ntsc load value 0fa 16 0fc 16 100 16 108 16 118 16 137 16 176 16 196 16 1/10000 1/4000 1/2000 1/1000 1/500 1/250 1/125 1/100 1/10156 1/4433 1/2084 1/1012 1/499 1/252 1/125 1/100 0c8 16 0ca 16 0ce 16 0d6 16 0e6 16 105 16 143 16 149 16 1/10000 1/4000 1/2000 1/1000 1/500 1/250 1/125 1/120 1/10101 1/4405 1/2070 1/1005 1/495 1/250 1/125 1/120 shutter speed calculated value load value shutter speed calculated value pal 2. low-speed shutter (valid during field accumulation mode only) shutter speed calculation formula n = 2 (1ff 16 ?l 16 ) fld however, "ff" cannot be used as the load value. load value 1fe 16 1fd 16 : : 101 16 100 16 2 4 : : 508 510 shutter speed (fld)
?11 CXD1265r 493 492 fld blk/vd hd xsg1 xsg2 id xv1 xv2 xv3 xv4 ccd pblk clp1 clp2 clp3 clp4 493 494 1 3579 2468 494 1 3579 2468 10 timing chart (1) ntsc vertical direction however, id is halted for black-and-white mode
?12 CXD1265r fld blk/vd hd xsg1 xsg2 id xv1 xv2 xv3 xv4 ccd pblk clp1 clp2 clp3 clp4 581 582 1 3579 2468 1 3579 2468 582 10 timing chart (2) pal vertical direction however, id is halted for black-and-white mode
?13 CXD1265r blk/hd cl h1 rg xshp xshd xsp1 xsp2 xsh1 xsh2 xdl1 xdl2 xv1 xv2 xv3 xv4 xsub clp1 clp2 clp3 clp4 pblk id bfg 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 155 160 170 180 96 35 7 14 31 38 44 51 53 62 31 35 71 80 75 81 86 89 98 103 80 114 135 140 140 140 113 timing chart (3) ntsc horizontal direction, analog color (gm = l, d2=l, test2 = l) black painted portions indicate the optical black output timing of ccd.
?14 CXD1265r blk/hd cl h1 rg xshp xshd xsp1 xsp2 xsh1 xsh2 xdl1 xdl2 xv1 xv2 xv3 xv4 xsub clp1 clp2 clp3 clp4 pblk id bfg 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 155 160 170 180 35 7 31 44 53 62 31 35 71 80 89 98 103 80 114 135 140 140 140 h l 113 h h l l 96 input pin 81 86 timing chart (4) ntsc horizontal direction, digital color 1 (gm = h, d2 = l, test2 = l) black painted portions indicate the optical black output timing of ccd.
?15 CXD1265r blk/hd cl h1 rg xshp xshd xsp1 xsp2 xsh1 xsh2 xdl1 xdl2 xv1 xv2 xv3 xv4 xsub clp1 clp2 clp3 clp4 pblk id bfg 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 155 160 170 180 96 35 7 31 44 53 62 31 35 71 80 81 86 89 98 103 80 114 135 140 140 140 h l input pin 113 timing chart (5) ntsc horizontal direction, digital color 2 (gm = h, d2 = l, test2 = h) black painted portions indicate the optical black output timing of ccd.
?16 CXD1265r blk/hd cl h1 rg xshp xshd xsp1 xsp2 xsh1 xsh2 xdl1 xdl2 xv1 xv2 xv3 xv4 xsub clp1 clp2 clp3 clp4 pblk id bfg 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 149 160 170 180 35 7 31 44 53 62 31 35 71 80 89 98 103 80 114 135 140 140 h l 113 ? 7 31 14 38 l l h h timing chart (6) eia horizontal direction, analog black-and-white (gm = l, d2 = h, test2 = l) black painted portions indicate the optical black output timing of ccd.
?17 CXD1265r blk/hd cl h1 rg xshp xshd xsp1 xsp2 xsh1 xsh2 xdl1 xdl2 xv1 xv2 xv3 xv4 xsub clp1 clp2 clp3 clp4 pblk id bfg 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 96 35 7 14 31 38 46 51 57 68 31 35 79 90 75 81 86 101 112 117 90 128 149 154 154 154 126 timing chart (7) pal horizontal direction, analog color (gm = l, d2 = l, test2 = l) black painted portions indicate the optical black output timing of ccd.
?18 CXD1265r blk/hd cl h1 rg xshp xshd xsp1 xsp2 xsh1 xsh2 xdl1 xdl2 xv1 xv2 xv3 xv4 xsub clp1 clp2 clp3 clp4 pblk id bfg 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 35 7 31 46 57 68 31 35 79 90 101 112 117 90 128 149 154 154 154 h l 126 h h l l 96 input pin 81 86 timing chart (8) pal horizontal direction, digital color 1 (gm = h, d2 = l, test2 = l) black painted portions indicate the optical black output timing of ccd.
?19 CXD1265r blk/hd cl h1 rg xshp xshd xsp1 xsp2 xsh1 xsh2 xdl1 xdl2 xv1 xv2 xv3 xv4 xsub clp1 clp2 clp3 clp4 pblk id bfg 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 96 35 7 31 46 57 68 31 35 79 90 81 86 101 112 117 90 128 149 154 154 154 h l input pin 126 timing chart (9) pal horizontal direction, digital color 2 (gm = h, d2 = l, test2 = h) black painted portions indicate the optical black output timing of ccd.
?20 CXD1265r blk/hd cl h1 rg xshp xshd xsp1 xsp2 xsh1 xsh2 xdl1 xdl2 xv1 xv2 xv3 xv4 xsub clp1 clp2 clp3 clp4 pblk id bfg 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 164 160 170 180 35 7 31 46 57 68 31 35 79 90 101 112 117 90 128 149 154 154 h l 126 ? 7 31 14 38 l l h h timing chart (10) ccir horizontal direction, analog black-and-white (gm = l, d2 = h, test2 = l) black painted portions indicate the optical black output timing of ccd.
?21 CXD1265r 22 578 hd xv1 xv2 xv3 xv4 xv1 xv2 xv3 xv4 xv1 xv2 xv3 xv4 xv1 xv2 xv3 xv4 xsg1 xsg2 3 36 33 36 36 36 36 36 3 odd even odd even 3 4-1. timing chart of readout (ntsc/eia) field readout frame readout unit: number of clocks (1ck = 69.84ns)
?22 CXD1265r 3 22 hd xv1 xv2 xv3 xv4 xv1 xv2 xv3 xv4 xv1 xv2 xv3 xv4 xv1 xv2 xv3 xv4 xsg1 xsg2 3 36 33 36 36 36 36 36 3 589 odd even odd even 4-2. timing chart of readout (pal/ccir) field readout frame readout unit: number of clocks (1ck = 70.48ns)
?23 CXD1265r ck cl h1 h2 rg xshp xshd xsp1 xsp2 xsh1 xsh2 xsh1 (shp) xsh2 (shd) xdl1 xdl2 mck for color mode * for black and white mode, xsp1, xsp2, xdl1, and xdl2 are halted. for black-and-white mode 5. high-speed clock timing chart
?24 CXD1265r package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package weight epoxy / phenol resin solder plating 42 alloy package structure 12.0 0.2 * 10.0 0.1 (0.22) 0.18 ?0.03 + 0.08 0.5 0.08 1 16 17 32 33 48 49 64 0.5 0.2 (11.0) 0.127 ?0.02 + 0.05 a 1.5 ?0.1 + 0.2 0.1 0.1 0.5 0.2 0?to 10 64pin lqfp (plastic) lqfp-64p-l01 * qfp064-p-1010-a 0.3g detail a 0.1 note: dimension * ?does not include mold protrusion.

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